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| SSM9972GI N-channel Enhancement-mode Power MOSFET PRODUCT SUMMARY BVDSS R DS(ON) ID DESCRIPTION The SSM9972GI achieves fast switching performance with low gate charge without a complex drive circuit. It is suitable for low voltage applications such as DC/DC converters and general switching circuits. 60V 18m 35A Pb-free; RoHS-compliant TO-220CFM The SSM9972GI is in TO-220CFM for through-hole mounting where a small footprint is required on the board, and/or an external heatsink is to be attached. G D S These devices are manufactured with an advanced process, providing improved on-resistance and switching performance. TO-220CFM (suffix I) ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID IDM PD Parameter Drain-source voltage Gate-source voltage Continuous drain current, TC = 25C TC = 100C Pulsed drain current 1 Value 60 25 35 22 120 31 0.25 Units V V A A A W W/C Total power dissipation, TC = 25C Linear derating factor TSTG TJ Storage temperature range Operating junction temperature range -55 to 150 -55 to 150 C C THERMAL CHARACTERISTICS Symbol RJC RJA Parameter Maximum thermal resistance, junction-case Maximum thermal resistance, junction-ambient Value 4 62 Units C/W C/W Notes: 1. Pulse width must be limited to avoid exceeding the safe operating area. 2. Pulse width <300us, duty cycle <2%. 9/20/2006 Rev.3.1 www.SiliconStandard.com 1 of 5 SSM9972GI ELECTRICAL CHARACTERISTICS Symbol BVDSS Parameter Drain-source breakdown voltage Breakdown voltage temperature coefficient (at Tj = 25C, unless otherwise specified) Test Conditions VGS=0V, ID= 250uA Reference to 25C, ID=1mA VGS=10V, ID=23A VGS=4.5V, ID=12A Min. 60 - Typ. 0.06 - Max. Units 18 22 V V/C m m BV DSS/Tj RDS(ON) Static drain-source on-resistance VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Rg Gate threshold voltage Forward transconductance VDS=VGS, ID=250uA VDS=10V, ID=23A 1 - 40 35 9.5 20 12 37 47 59 280 230 1.6 3 10 25 100 56 2.4 V S uA uA nA nC nC nC ns ns ns ns pF pF pF Drain-source leakage current VDS=60V, VGS=0V VDS=48V ,VGS=0V, Tj = 150C VGS=25V ID=23A VDS=48V VGS=4.5V VDS=30V ID=35A RG=3.3 , VGS=10V RD=0.86 VGS=0V VDS=25V f=1.0MHz f=1.0MHz Gate-source leakage current Total gate charge 2 Gate-source charge Gate-drain ("Miller") charge Turn-on delay time Rise time Turn-off delay time Fall time Input capacitance Output capacitance Reverse transfer capacitance Gate resistance 2 3160 5060 Source-Drain Diode Symbol VSD t rr Q rr Parameter Forward voltage 2 Test Conditions IS= 23A, VGS=0V Min. - Typ. - Max. Units 1.2 V Reverse recovery time Reverse recovery charge IS=23A, VGS=0V, dI/dt=100A/s - 36 45 - ns nC Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150C. 2.Pulse width <300us, duty cycle <2%. 9/20/2006 Rev.3.1 www.SiliconStandard.com 2 of 5 SSM9972GI 120 120 10V 7.0V T C = 150 C ID , Drain Current (A) ID , Drain Current (A) 90 10V 7.0V o 90 T C =25 C o 5.0V 60 5.0V 60 4.5V 4.5V 30 30 V G =3.0V V G =3.0V 0 0 0 2 4 6 8 0 2 4 6 8 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 20 1.6 I D = 12 A T C =25 o C 18 1.4 I D =23A V G =10V Normalized RDS(ON) 2 4 6 8 10 RDS(ON) (m ) 1.2 1.0 16 0.8 14 0.6 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 1.7 20 15 Normalized VGS(th) (V) T j =150 o C IS(A) 10 T j =25 o C 1.2 0.7 5 0 0 0.2 0.4 0.6 0.8 1 1.2 0.2 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode Fig 6. Gate Threshold Voltage vs. Junction Temperature 9/20/2006 Rev.3.1 www.SiliconStandard.com 3 of 5 SSM9972GI 12 f=1.0MHz 10000 I D = 23 A VGS , Gate to Source Voltage (V) 10 8 V DS =48V V DS =38V V DS =30V C (pF) 1000 C iss 6 4 2 C oss C rss 0 0 20 40 60 80 100 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 1000 1 Normalized Thermal Response (R thjc) Duty factor=0.5 100 0.2 ID (A) 100us 10 0.1 0.1 0.05 1 T C =25 C Single Pulse o 1ms 10ms 100ms DC PDM 0.02 t T 0.01 Single Pulse Duty factor = t/T Peak Tj = PDM x Rthjc + TC 0.1 0.1 1 10 100 1000 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance 100 V DS =5V 80 VG QG 4.5V T j =25 o C ID , Drain Current (A) 60 T j =150 o C QGS 40 QGD 20 Charge 0 Q 0 2 4 6 8 V GS , Gate-to-Source Voltage (V) Fig 11. Transfer Characteristics 9/20/2006 Rev.3.1 Fig 12. Gate Charge Waveform www.SiliconStandard.com 4 of 5 SSM9972GI PHYSICAL DIMENSIONS - TO-220CFM E A SYMBOLS Millimeters MIN NOM MAX c2 A A1 4.30 2.30 0.50 0.95 0.45 2.30 9.70 ------- 4.60 2.65 0.70 1.20 0.65 2.60 4.90 3.00 0.90 1.50 0.80 2.90 b b1 c c2 E L4 L4 10.00 10.40 3.20 2.54 ------- 14.70 15.40 16.10 e 1. All dimensions are in millimeters. b1 A1 2. Dimension do not include mold protrusions. b c e PART MARKING - TO-220 PACKING: Moisture sensitivity level MSL3 1000pcs in tubes packed inside a moisture barrier bag (MBB). 9972GI YWWSSS PART NUMBER: 9972GI = SSM9972GI DATE/LOT CODE: Y = last digit of the year WW = work week (01 -> 52) SSS = lot code sequence Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 9/20/2006 Rev.3.1 www.SiliconStandard.com 5 of 5 |
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